Synopsys Synplify with Design Planner L-2016.03-SP1 - Download

Description

Synopsys Synplify software is the industry standard for producing high-performance, cost-effective FPGA designs. Synplify supports the latest VHDL and Verilog language structures, including SystemVerilog and VHDL-2008. The software also supports FPGA architecture from various FPGA vendors, including Altera, Achronix, Lattice, Microsemi, and Xilinx. Synplify software uses a simple interface and is capable of performing HDL code plug-ins and visual analysis.

Features and Features of Synopsys Synplify:

Automatic compilation of additional flow points 4 times faster
Acceleration runtime with support for up to 4 processors
TCL script support for automated flow and adjustable mixing, debugging and reporting
Optimal area and time results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
Manage multiple design applications for large design team projects
Custom mapping software for each FPGA device ensures optimal performance
Conclusions Automatic memory and DSP filling of the plan with the desired area ensures the power and quality of the results time.
FSM extraction, optimization and debugging with user control
Detectable and controllable flow with control that limits combination optimization.
Integration with VCS simulation to analyze simulation data
Generates high-quality data for power optimization
ASIC language tool and SDC compatibility limitation
A process management interface for tracking design progress and errors
Geographic distribution/project synchronization with multiple devices

click here for complete Synopsys Synplify information.

required system

System requirements: PC/Linux
Supported operating systems: Windows 7even / 8.x | RHEL 5-7 (Red Hat Enterprise Linux) / SLES 11 or 12 (SUSE Linux Enterprise Server)